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| LTC1403-1/LTC1403A-1 Serial 12-Bit/14-Bit, 2.8Msps Sampling ADCs with Shutdown FEATURES s s s s s s s s s s DESCRIPTIO 2.8Msps Conversion Rate Low Power Dissipation: 14mW 3V Single Supply Operation 2.5V Internal Bandgap Reference can be Overdriven 3-Wire Serial Interface Sleep (10W) Shutdown Mode Nap (3mW) Shutdown Mode 80dB Common Mode Rejection 1.25V Bipolar Input Range Tiny 10-Lead MSE Package The LTC(R)1403-1/LTC1403A-1 are 12-bit/14-bit, 2.8Msps serial ADCs with differential inputs. The devices draw only 4.7mA from a single 3V supply and come in a tiny 10-lead MSE package. A Sleep shutdown feature lowers power consumption to 10W. The combination of speed, low power and tiny package makes the LTC1403-1/LTC1403A-1 suitable for high speed, portable applications. The 80dB common mode rejection allows users to eliminate ground loops and common mode noise by measuring signals differentially from the source. The devices convert -1.25V to 1.25V bipolar inputs differentially. The absolute voltage swing for +AIN and -AIN extends from ground to the supply voltage. The serial interface sends out the conversion results during the 16 clock cycles following CONV for compatibility with standard serial interfaces. If two additional clock cycles for acquisition time are allowed after the data stream in between conversions, the full sampling rate of 2.8Msps can be achieved with a 50.4MHz clock. , LTC and LT are registered trademarks of Linear Technology Corporation. APPLICATIO S s s s s s Communications Data Acquisition Systems Uninterrupted Power Supplies Multiphase Motor Control Multiplexed Data Acquisition BLOCK DIAGRA 10F 3V LTC1403A-1 AIN+ AIN- 1 7 VDD 14-BIT LATCH THREESTATE SERIAL OUTPUT PORT 14 + S&H 14-BIT ADC THD, 2nd, 3rd (dB) 8 SDO 2 - VREF 2.5V REFERENCE 3 10F 4 10 TIMING LOGIC 9 6 11 EXPOSED PAD CONV GND 5 SCK 14031 BD U THD, 2nd and 3rd vs Input Frequency for Differential Input Signals -44 -50 -56 -62 -68 -74 -80 -86 -92 -98 -104 0.1 1 10 FREQUENCY (MHz) 100 14031 G19 W U THD 3rd 2nd 14031f 1 LTC1403-1/LTC1403A-1 ABSOLUTE (Notes 1, 2) AXI U RATI GS PACKAGE/ORDER I FOR ATIO ORDER PART NUMBER TOP VIEW AIN+ AIN- VREF GND GND 1 2 3 4 5 10 9 8 7 6 CONV SCK SDO VDD GND Supply Voltage (VDD) ................................................. 4V Analog Input Voltage (Note 3) ....................................-0.3V to (VDD + 0.3V) Digital Input Voltage ................... - 0.3V to (VDD + 0.3V) Digital Output Voltage .................. - 0.3V to (VDD + 0.3V) Power Dissipation .............................................. 100mW Operation Temperature Range LTC1403C-1/LTC1403AC-1 ..................... 0C to 70C LTC1403I-1/LTC1403AI-1 .................. - 40C to 85C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C 11 LTC1403CMSE-1 LTC1403IMSE-1 LTC1403ACMSE-1 LTC1403AIMSE-1 MSE PART MARKING LTBGP LTBGQ LTBGR LTBGS MSE PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 125C, JA = 150C/ W EXPOSED PAD (PIN 11) IS GND MUST BE SOLDERED TO PCB Consult LTC Marketing for parts specified with wider operating temperature ranges. CO VERTER CHARACTERISTICS PARAMETER Resolution (No Missing Codes) Integral Linearity Error Offset Error Gain Error Gain Tempco (Notes 4, 5, 18) (Notes 4, 18) (Note 4, 18) CONDITIONS The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. With internal reference. VDD = 3V MIN q q q q LTC1403-1 TYP MAX 0.25 1 5 15 1 2 10 30 LTC1403A-1 MIN TYP MAX 14 -4 -20 -60 0.5 2 10 15 1 4 20 60 UNITS Bits LSB LSB LSB ppm/C ppm/C 12 -2 -10 -30 Internal Reference (Note 4) External Reference A ALOG I PUT SYMBOL PARAMETER VIN VCM IIN CIN tACQ tAP tJITTER CMRR The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VDD = 3V CONDITIONS 2.7V VDD 3.3V q MIN TYP -1.25 to 1.25 0 to VDD MAX UNITS V V Analog Differential Input Range (Notes 3, 8, 9) Analog Common Mode + Differential Input Range (Note 10) Analog Input Leakage Current Analog Input Capacitance Sample-and-Hold Acquisition Time Sample-and-Hold Aperture Delay Time Sample-and-Hold Aperture Delay Time Jitter Analog Input Common Mode Rejection Ratio q 1 13 39 1 0.3 (Note 6) q fIN = 1MHz, VIN = 0V to 3V fIN = 100MHz, VIN = 0V to 3V -60 -15 2 U A pF ns ns ps dB dB 14031f W U U WW W U U U LTC1403-1/LTC1403A-1 DY A IC ACCURACY SYMBOL SINAD PARAMETER Signal-to-Noise Plus Distortion Ratio The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VDD = 3V. Single-ended AIN+ signal drive with AIN- = 1.5V DC. Differential signal drive with VCM = 1.5V at AIN+ and AIN- CONDITIONS 100kHz Input Signal (Note 19) 1.4MHz Input Signal (Note 19) 100kHz Input Signal, External VREF = 3.3V, VDD 3.3V (Note 19) 750kHz Input Signal, External VREF = 3.3V, VDD 3.3V (Note 19) 100kHz First 5 Harmonics (Note 19) 1.4MHz First 5 Harmonics (Note 19) 100kHz Input Signal (Note 19) 1.4MHz Input Signal (Note 19) 0.625VP-P 1.4MHz Summed with 0.625VP-P 1.56MHz into AIN+ and Inverted into AIN- VREF = 2.5V (Note 18) VIN = 2.5VP-P, SDO = 11585LSBP-P (Note 15) S/(N + D) 68dB q THD SFDR IMD I TER AL REFERE CE CHARACTERISTICS PARAMETER VREF Output Voltage VREF Output Tempco VREF Line Regulation VREF Output Resistance VREF Settling Time CONDITIONS IOUT = 0 The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VDD = 3V MIN TYP 2.5 15 VDD = 2.7V to 3.6V, VREF = 2.5V Load Current = 0.5mA 600 0.2 2 MAX UNITS V ppm/C V/V ms DIGITAL I PUTS A D DIGITAL OUTPUTS SYMBOL VIH VIL IIN CIN VOH VOL IOZ COZ ISOURCE ISINK PARAMETER High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage Low Level Output Voltage Hi-Z Output Leakage DOUT Hi-Z Output Capacitance DOUT Output Short-Circuit Source Current Output Short-Circuit Sink Current VOUT = 0V, VDD = 3V VOUT = VDD = 3V CONDITIONS VDD = 3.3V VDD = 2.7V VIN = 0V to VDD (Note 20) The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VDD = 3V MIN q q q U U U WU U MIN 68 LTC1403-1 TYP MAX 70.5 70.5 72 72 -87 -83 -87 -83 -82 0.25 50 5 LTC1403A-1 MIN TYP MAX 70 73.5 73.5 76.3 76.3 -90 -86 -90 -86 -82 1 50 5 UNITS dB dB dB dB dB dB dB dB dB LSBRMS MHz MHz Total Harmonic Distortion Spurious Free Dynamic Range Intermodulation Distortion Code-to-Code Transition Noise Full Power Bandwidth Full Linear Bandwidth q -76 -78 U TYP MAX 0.6 10 UNITS V V A pF V V V A pF mA mA 14031f 2.4 5 q q q VDD = 3V, IOUT = - 200A VDD = 2.7V, IOUT = 160A VDD = 2.7V, IOUT = 1.6mA VOUT = 0V to VDD 2.5 2.9 0.05 0.10 1 20 15 0.4 10 3 LTC1403-1/LTC1403A-1 POWER REQUIRE E TS SYMBOL VDD IDD PARAMETER Supply Voltage Positive Supply Voltage The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 17) CONDITIONS Active Mode Nap Mode Sleep Mode (LTC1403) Sleep Mode (LTC1403A) Active Mode with SCK in Fixed State (Hi or Lo) q q PD Power Dissipation The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VDD = 3V SYMBOL fSAMPLE(MAX) tTHROUGHPUT tSCK tCONV t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t12 PARAMETER Maximum Sampling Frequency per Channel (Conversion Rate) Minimum Sampling Period (Conversion + Acquisiton Period) Clock Period Conversion Time Minimum Positive or Negative SCLK Pulse Width CONV to SCK Setup Time Nearest SCK Edge Before CONV Minimum Positive or Negative CONV Pulse Width SCK to Sample Mode CONV to Hold Mode 16th SCK to CONV Interval (Affects Acquisition Period) Minimum Delay from SCK to Valid Data SCK to Hi-Z at SDO Previous SDO Bit Remains Valid After SCK VREF Settling Time After Sleep-to-Wake Transition CONDITIONS q q TI I G CHARACTERISTICS Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to GND. Note 3: When these pins are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below GND or greater than VDD without latchup. Note 4: Offset and full-scale specifications are measured for a singleended AIN+ input with AIN- grounded and using the internal 2.5V reference. Note 5: Integral linearity is tested with an external 2.55V reference and is defined as the deviation of a code from the straight line passing through the actual endpoints of a transfer curve. The deviation is measured from the center of quantization band. Note 6: Guaranteed by design, not subject to test. Note 7: Recommended operating conditions. Note 8: The analog input range is defined for the voltage difference between AIN+ and AIN-. Performance is specified with AIN- = 1.5V DC while driving AIN+. Note 9: The absolute voltage at AIN+ and AIN- must be within this range. Note 10: If less than 3ns is allowed, the output data will appear one clock cycle later. It is best for CONV to rise half a clock before SCK, when running the clock at rated speed. 4 UW MIN 2.7 TYP 4.7 1.1 2 2 12 MAX 3.6 7 1.5 15 10 UNITS V mA mA A A mW UW MIN 2.8 TYP MAX UNITS MHz ns ns SCLK cycles ns ns ns ns ns ns ns ns ns ns ms (Note 16) (Note 6) (Note 6) (Notes 6, 10) (Note 6) (Note 6) (Note 6) (Notes 6, 11) (Notes 6, 7, 13) (Notes 6, 12) (Notes 6, 12) (Notes 6, 12) (Notes 6, 14) q 19.8 16 2 3 0 4 4 1.2 45 8 6 2 357 10000 18 2 Note 11: Not the same as aperture delay. Aperture delay is smaller (1ns) because the 2.2ns delay through the sample-and-hold is subtracted from the CONV to Hold mode delay. Note 12: The rising edge of SCK is guaranteed to catch the data coming out into a storage latch. Note 13: The time period for acquiring the input signal is started by the 16th rising clock and it is ended by the rising edge of convert. Note 14: The internal reference settles in 2ms after it wakes up from Sleep mode with one or more cycles at SCK and a 10F capacitive load. Note 15: The full power bandwidth is the frequency where the output code swing drops to 3dB with a 2.5VP-P input sine wave. Note 16: Maximum clock period guarantees analog performance during conversion. Output data can be read without an arbitrarily long clock. Note 17: VDD = 3V, fSAMPLE = 2.8Msps. Note 18: The LTC1403A-1 is measured and specified with 14-bit Resolution (1LSB = 152V) and the LTC1403-1 is measured and specified with 12-bit Resolution (1LSB = 610V). Note 19: Full-scale sinewaves are fed into the noninverting input while the inverting input is kept at 1.5V DC. Note 20: The sampling capacitor at each input accounts for 4.1pF of the input capacitance. 14031f LTC1403-1/LTC1403A-1 TA = 25C, VDD = 3V. Single ended AIN+ signal drive with AIN- = 1.5V DC, differential signals drive both inputs with VCM = 1.5V DC (LTC1403A-1) ENOBs and SINAD vs Input Frequency 12.0 11.5 11.0 74 71 68 65 62 59 56 53 1 10 FREQUENCY (MHz) 50 100 14031 G01 TYPICAL PERFOR A CE CHARACTERISTICS 10.0 9.5 9.0 8.5 8.0 0.1 -74 -80 -86 -92 -98 -104 0.1 THD 3rd 2nd SFDR (dB) 100 14031 G02 10.5 THD, 2nd, 3rd (dB) ENOBs (BITS) SNR vs Input Frequency 74 71 68 12.0 11.5 11.0 SNR (dB) 65 62 59 56 53 50 0.1 1 10 FREQUENCY (MHz) 100 14031 G04 10.5 10.0 9.5 9.0 8.5 8.0 0.1 1 10 FREQUENCY (MHz) 65 62 59 56 53 50 100 14031 G18 THD, 2nd, 3rd (dB) ENOBs (BITS) SFDR vs Input Frequency for Differential Input Signals 104 98 92 MAGNITUDE (dB) MAGNITUDE (dB) 86 SFDR (dB) 80 74 68 62 56 50 44 0.1 1 10 FREQUENCY (MHz) 100 14031 G20 UW THD, 2nd and 3rd vs Input Frequency -44 -50 -56 -62 -68 SFDR vs Input Frequency 104 98 92 86 80 74 68 62 56 50 SINAD (dB) 1 10 FREQUENCY (MHz) 44 0.1 1 10 FREQUENCY (MHz) 100 14031 G03 ENOBs and SINAD vs Input Frequency for Differential Input Signals 74 71 68 THD, 2nd and 3rd vs Input Frequency for Differential Input Signals -44 -50 -56 -62 -68 -74 -80 -86 -92 -98 -104 0.1 1 10 FREQUENCY (MHz) 100 14031 G19 SINAD (dB) THD 3rd 2nd 98kHz Sine Wave 4096 Point FFT Plot 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 350 700k 1.05M FREQUENCY (Hz) 1.4M 14031 G05 1.3MHz Sine Wave 4096 Point FFT Plot 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 350k 700k 1.05M FREQUENCY (Hz) 1.4M 14031 G06 14031f 5 LTC1403-1/LTC1403A-1 TA = 25C, VDD = 3V. Single ended AIN+ signal drive with AIN- = 1.5V DC, differential signals drive both inputs with VCM = 1.5V DC (LTC1403A-1) 1.4MHz Input Summed with 1.56MHz Input IMD 4096 Point FFT Plot for Differential Input Signals 0 -10 -20 -30 0 -10 -20 MAGNITUDE (dB) TYPICAL PERFOR A CE CHARACTERISTICS MAGNITUDE (dB) -40 -50 -60 -70 -80 -90 -100 -110 -120 0 200k 400k 600k 800k 1M FREQUENCY (Hz) 1.2M 1.4M 14031 G07 MAGNITUDE (dB) Differential Linearity vs Output Code 1.0 0.8 4 3 DIFFERENTIAL LINEARITY (LSB) INTEGRAL LINEARITY (LSB) 2 1 0 -1 -2 -3 -4 INTEGRAL LINEARITY (LSB) 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 4096 12288 8192 OUTPUT CODE 16384 14031 G08 Differential and Integral Linearity vs Conversion Rate 8 7 6 5 LINEARITY (LSB) 4 3 2 1 0 -1 -2 -3 -4 2 2.25 2.5 2.75 3 3.25 3.5 3.75 CONVERSION RATE (Msps) 4 MIN INL MAX DNL MIN DNL S/(N+D) (dB) 18 CLOCKS PER CONVERSION 6 UW 1.3MHz Sine Wave 4096 Point FFT Plot for Differential Input Signals 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 350 700k 1.05M FREQUENCY (Hz) 1.4M 14031 G21 10.7MHz Sine Wave 4096 Point FFT Plot for Differential Input Signals -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 350 700k 1.05M FREQUENCY (Hz) 1.4M 14031 G22 Integral Linearity vs Output Code 4 3 2 1 0 -1 -2 -3 0 4096 12288 8192 OUTPUT CODE -4 16384 14071 G09 Integral Linearity vs Output Code for Differential Input Signals 0 4096 12288 8192 OUTPUT CODE 16384 14071 G23 SINAD vs Conversion Rate 78 77 76 MAX INL 75 74 73 72 71 70 69 68 2 EXTERNAL VREF = 3.3V fIN ~ fS/3 EXTERNAL VREF = 3.3V fIN ~ fS/40 INTERNAL VREF = 2.5V fIN ~ fS/3 INTERNAL VREF = 2.5V fIN ~ fS/40 2.25 2.5 2.75 3 3.25 3.5 3.75 CONVERSION RATE (Msps) 4 14031 G10 14031 G11 14031f LTC1403-1/LTC1403A-1 TYPICAL PERFOR A CE CHARACTERISTICS 2.5VP-P Power Bandwidth 12 6 0 AMPLITUDE (dB) CMRR (dB) PSRR (dB) -6 -12 -18 -24 -30 -36 1M 10M 100M FREQUENCY (Hz) 1G 14031 G12 Reference Voltage vs Load Current 2.4902 2.4900 2.4898 VREF (V) VDD SUPPLY CURRENT (mA) VREF (V) 2.4896 2.4894 2.4892 2.4890 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 LOAD CURRENT (mA) 14031 G15 UW TA = 25C, VDD = 3V (LTC1403-1 and LTC1403A-1) PSRR vs Frequency -25 -30 CMRR vs Frequency 0 -20 -35 -40 -60 -80 -100 -40 -45 -50 -55 -60 -65 -120 100 -70 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M 1 10 100 1k 10k FREQUENCY (Hz) 100k 1M 14031 G13 14031 G14 Reference Voltage vs VDD 2.4902 2.4900 2.4898 2.4896 2.4894 2.4892 2.4890 2.6 2.8 3.0 3.2 VDD (V) 3.4 3.6 14031 G16 VDD Supply Current vs Conversion Rate 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 CONVERSION RATE (Msps) 14031 G17 14031f 7 LTC1403-1/LTC1403A-1 PI FU CTIO S AIN+ (Pin 1): Noninverting Analog Input. AIN+ operates fully differentially with respect to AIN- with a -1.25V to 1.25V differential swing with respect to AIN- and a 0V to VDD common mode swing. AIN- (Pin 2): Inverting Analog Input. AIN- operates fully differentially with respect to AIN+ with a 1.25V to -1.25V differential swing with respect to AIN+ and a 0V to VDD common mode swing. VREF (Pin 3): 2.5V Internal Reference. Bypass to GND and to a solid analog ground plane with a 10F ceramic capacitor (or 10F tantalum in parallel with 0.1F ceramic). Can be overdriven by an external reference between 2.55V and VDD. GND (Pins 4, 5, 6, 11): Ground and Exposed Pad. These ground pins and the exposed pad must be tied directly to the solid ground plane under the part. Keep in mind that analog signal currents and digital output signal currents flow through these pins. VDD (Pin 7): 3V Positive Supply. This single power pin supplies 3V to the entire chip. Bypass to GND and to a solid analog ground plane with a 10F ceramic capacitor (or 10F tantalum in parallel with 0.1F ceramic). Keep in mind that internal analog currents and digital output signal currents flow through this pin. Care should be taken to place the 0.1F bypass capacitor as close to Pins 6 and 7 as possible. SDO (Pin 8): Three-State Serial Data Output. Each of output data words represents the difference between AIN+ and AIN- analog inputs at the start of the previous conversion. The output format is 2's complement. SCK (Pin 9): External Clock Input. Advances the conversion process and sequences the output data on the rising edge. Responds to TTL (3V) and 3V CMOS levels. One or more pulses wake from sleep. CONV (Pin 10): Convert Start. Holds the analog input signal and starts the conversion on the rising edge. Responds to TTL (3V) and 3V CMOS levels. Two pulses with SCK in fixed high or fixed low state start Nap mode. Four or more pulses with SCK in fixed high or fixed low state start Sleep mode. BLOCK DIAGRA 1 + S&H 14-BIT ADC 14-BIT LATCH AIN+ AIN- 10F 4 GND 5 6 8 W U U U 10F 3V LTC1403A-1 7 VDD THREESTATE SERIAL OUTPUT PORT 14 8 SDO 2 - VREF 2.5V REFERENCE 3 10 TIMING LOGIC 9 11 EXPOSED PAD CONV SCK 14031 BD 14031f LTC1403-1/LTC1403A-1 TI I G DIAGRA 17 SCK t4 CONV t6 INTERNAL S/H STATUS SAMPLE t8 SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION SDO Hi-Z D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X* X* Hi-Z 14031 TD01 18 *BITS MARKED "X" AFTER D0 SHOULD BE IGNORED. 17 SCK t4 CONV t6 INTERNAL S/H STATUS 18 SAMPLE t8 SDO SLK t1 CONV t1 NAP SLEEP t12 VREF 14031 TD02 NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS W LTC1403 Timing Diagram t2 t3 1 2 3 4 5 6 7 t1 8 9 10 11 12 13 14 15 16 t7 17 18 1 t5 tACQ HOLD t8 SAMPLE t9 HOLD 14-BIT DATA WORD tCONV tTHROUGHPUT UW LTC1403A Timing Diagram t2 t3 1 2 3 4 5 6 7 t1 8 9 10 11 12 13 14 15 16 t7 17 18 1 t5 tACQ HOLD t8 SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION Hi-Z D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Hi-Z 14031 TD01b SAMPLE t9 HOLD 14-BIT DATA WORD tCONV tTHROUGHPUT Nap Mode and Sleep Mode Waveforms SCK to SDO Delay SCK t8 t10 SDO VOH VOL 14031 TD03 VIH SCK VIH t9 90% SDO 10% 14031f 9 LTC1403-1/LTC1403A-1 APPLICATIO S I FOR ATIO DRIVING THE ANALOG INPUT The differential analog inputs of the LTC1403-1/LTC1403A-1 are easy to drive. The inputs may be driven differentially or as a single-ended input (i.e., the AIN- input is set to VCM). Both differential analog inputs, AIN+ with AIN-, are sampled at the same instant. Any unwanted signal that is common to both inputs of each input pair will be reduced by the common mode rejection of the sample-and-hold circuit. The inputs draw only one small current spike while charging the sample-and-hold capacitors at the end of conversion. During conversion, the analog inputs draw only a small leakage current. If the source impedance of the driving circuit is low, then the LTC1403-1/ LTC1403A-1 inputs can be driven directly. As source impedance increases, so will acquisition time. For minimum acquisition time with high source impedance, a buffer amplifier must be used. The main requirement is that the amplifier driving the analog input(s) must settle after the small current spike before the next conversion starts (settling time must be 39ns for full throughput rate). Also keep in mind while choosing an input amplifier, the amount of noise and harmonic distortion added by the amplifier. CHOOSING AN INPUT AMPLIFIER Choosing an input amplifier is easy if a few requirements are taken into consideration. First, to limit the magnitude of the voltage spike seen by the amplifier from charging the sampling capacitor, choose an amplifier that has a low output impedance (<100) at the closed-loop bandwidth frequency. For example, if an amplifier is used with a gain of 1 and has a unity-gain bandwidth of 50MHz, then the output impedance at 50MHz must be less than 100. The second requirement is that the closed-loop bandwidth must be greater than 40MHz to ensure adequate small-signal settling for full throughput rate. If slower op amps are used, more time for settling can be provided by increasing the time between conversions. The best choice for an op amp to drive the LTC1403-1/LTC1403A-1 will depend on the application. Generally, applications fall into two categories: AC applications where dynamic specifications are most critical and time domain applications where DC accuracy and settling time are most critical. The following list is a summary of the op amps that are suitable for driving the LTC1403-1/LTC1403A-1. 10 U (More detailed information is available in the Linear Technology Databooks and our website at www.linear.com.) LTC(R)1566-1: Low Noise 2.3MHz Continuous Time LowPass Filter. LT1630: Dual 30MHz Rail-to-Rail Voltage FB Amplifier. 2.7V to 15V supplies. Very high AVOL, 500V offset and 520ns settling to 0.5LSB for a 4V swing. THD and noise are -93dB to 40kHz and below 1LSB to 320kHz (AV = 1, 2VP-P into 1k, VS = 5V), making the part excellent for AC applications (to 1/3 Nyquist) where rail-to-rail performance is desired. Quad version is available as LT1631. LT1632: Dual 45MHz Rail-to-Rail Voltage FB Amplifier. 2.7V to 15V supplies. Very high AVOL, 1.5mV offset and 400ns settling to 0.5LSB for a 4V swing. It is suitable for applications with a single 5V supply. THD and noise are -93dB to 40kHz and below 1LSB to 800kHz (AV = 1, 2VP-P into 1k, VS = 5V), making the part excellent for AC applications where rail-to-rail performance is desired. Quad version is available as LT1633. LT1813: Dual 100MHz 750V/s 3mA Voltage Feedback Amplifier. 5V to 5V supplies. Distortion is -86dB to 100kHz and -77dB to 1MHz with 5V supplies (2VP-P into 500). Excellent part for fast AC applications with 5V supplies. LT1801: 80MHz GBWP, -75dBc at 500kHz, 2mA/Amplifier, 8.5nV/Hz. LT1806/LT1807: 325MHz GBWP, -80dBc Distortion at 5MHz, Unity-Gain Stable, R-R In and Out, 10mA/Amplifier, 3.5nV/Hz. LT1810: 180MHz GBWP, -90dBc Distortion at 5MHz, Unity-Gain Stable, R-R In and Out, 15mA/Amplifier, 16nV/Hz. LT1818/LT1819: 400MHz, 2500V/s,9mA, Single/Dual Voltage Mode Operational Amplifier. LT6200: 165MHz GBWP, -85dBc Distortion at 1MHz, UnityGain Stable, R-R In and Out, 15mA/Amplifier, 0.95nV/Hz. LT6203: 100MHz GBWP, -80dBc Distortion at 1MHz, Unity-Gain Stable, R-R In and Out, 3mA/Amplifier, 1.9nV/Hz. LT6600-10: Amplifier/Filter Differential In/Out with 10MHz Cutoff. 14031f W U U LTC1403-1/LTC1403A-1 APPLICATIO S I FOR ATIO INPUT FILTERING AND SOURCE IMPEDANCE The noise and the distortion of the input amplifier and other circuitry must be considered since they will add to the LTC1403-1/LTC1403A-1 noise and distortion. The small-signal bandwidth of the sample-and-hold circuit is 50MHz. Any noise or distortion products that are present at the analog inputs will be summed over this entire bandwidth. Noisy input circuitry should be filtered prior to the analog inputs to minimize noise. A simple 1-pole RC filter is sufficient for many applications. For example, Figure 1 shows a 47pF capacitor from AIN+ to ground and a 51 source resistor to limit the input bandwidth to 47MHz. The 47pF capacitor also acts as a charge reservoir for the input sample-and-hold and isolates the ADC input from sampling-glitch sensitive circuitry. High quality capacitors and resistors should be used since these components can add distortion. NPO and silvermica type dielectric capacitors have excellent linearity. Carbon surface mount resistors can generate distortion from self heating and from damage that may occur during soldering. Metal film surface mount resistors are much less susceptible to both problems. When high amplitude unwanted signals are close in frequency to the desired signal frequency, a multiple pole filter is required. High external source resistance, combined with the 13pF of input capacitance, will reduce the rated 50MHz bandwidth and increase acquisition time beyond 39ns. 51 47pF VCM 1.5V DC 2 AIN- LTC1403-1/ LTC1403A-1 3 VREF GND 1403A F01 1 AIN+ 10F 11 Figure 1. RC Input Filter INPUT RANGE The analog inputs of the LTC1403-1/LTC1403A-1 may be driven fully differentially with a single supply. Each input may swing up to 3VP-P individually. In the conversion range, each input is always up to 1.25V more positive or more negative than the inverting input of each channel. U The 1.25V range is also ideally suited for AC-coupled signals in single supply applications. Figure 2 shows how to AC couple signals in a single supply system without needing a mid-supply 1.5V external reference. The DC common mode level is supplied by the previous stage that is already bounded by the single supply voltage of the system. The common mode range of the inputs extend from ground to the supply voltage VDD. If the difference between the AIN+ and AIN- inputs exceeds 1.25V, the output code will stay fixed at zero and all ones and if this difference goes below -1.25V, the output code will stay fixed at one and all zeros. C2 1F LTC1403-1/ LTC1403A-1 1 AIN+ 2 AIN- 3 VREF 14031 F02 W U U R3 51 VIN C3 56pF R2 1.6k R1 1.6k C1 C4 1F 10F + C1, C2: FILM TYPE C3: COG TYPE C4: CERAMIC BYPASS Figure 2. AC Coupling of AC Signals with 1kHz Low Cut INTERNAL REFERENCE The LTC1403-1/LTC1403A-1 has an on-chip, temperature compensated, bandgap reference that is factory trimmed near 2.5V to obtain 1.25V input span. The reference amplifier output VREF, (Pin 3) must be bypassed with a capacitor to ground. The reference amplifier is stable with capacitors of 1F or greater. For the best noise performance, a 10F ceramic or a 10F tantalum in parallel with a 0.1F ceramic is recommended. The VREF pin can be overdriven with an external reference as shown in Figure 3. The voltage of the external reference must be higher than the 2.5V of the class A pull-up output of the internal 3VREF 10F 3 VREF LTC1403-1/ LTC1403A-1 11 GND 14031 F03 Figure 3 14031f 11 LTC1403-1/LTC1403A-1 APPLICATIO S I FOR ATIO reference. The recommended range for an external reference is 2.55V to VDD. An external reference at 2.55V will see a DC quiescent load of 0.75mA and as much as 3mA during conversion. INPUT SPAN VERSUS REFERENCE VOLTAGE The differential input range has a unipolar voltage span that equals the difference between the voltage at the reference buffer output VREF at Pin 3, and the voltage at the ground (Exposed Pad Ground). The differential input range of the ADC is 1.25V when using the internal reference. The internal ADC is referenced to these two nodes. This relationship also holds true with an external reference. DIFFERENTIAL INPUTS The LTC1403-1/LTC1403A-1 have a unique differential sample-and-hold circuit that allows inputs from ground to VDD. The ADC will always convert the bipolar difference of AIN+ - AIN-, independent of the common mode voltage at the inputs. The common mode rejection holds up at extremely high frequencies, see Figure 4. The only requirement is that both inputs not go below ground or exceed VDD. Integral nonlinearity errors (INL) and differential nonlinearity errors (DNL) are largely independent of the common mode voltage. However, the offset error will vary. The change in offset error is typically less than 0.1% of the common mode voltage. CMRR vs Frequency 0 -20 -40 CMRR (dB) -60 -80 -100 -120 100 2'S COMPLEMENT OUTPUT CODE R4 499 R3 499 -5V C4 1F U2 1/2 LT1819 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M 14031 F04 Figure 4 Figure 6a. The LT1819 Driving the LTC1403A-1 Differentially 14031f 12 + VIN 1.25VP-P MAX + - - U Figure 5 shows the ideal input/output characteristics for the LTC1403-1/LTC1403A-1. The code transitions occur midway between successive integer LSB values (i.e., 0.5LSB, 1.5LSB, 2.5LSB, FS - 1.5LSB). The output code is natural binary with 1LSB = 2.5V/16384 = 153V for the LTC1403A-1, and 1LSB = 2.5V/4096 = 610V for the LTC1403-1. The LTC1403A-1 has 1LSB RMS of random white noise. Figure 6a shows the LTC1819 converting a single ended input signal to differential input signals for optimum THD and SFDR performance as shown in the FFT plot (Figure 6b). LTC1403-1/LTC1403A-1 Transfer Characteristic 011...111 011...110 011...101 100...010 100...001 100...000 -FS INPUT VOLTAGE (V) 14031 F05 W U U FS - 1LSB Figure 5 5V C5 0.1F C3 1F U1 1/2 LT1819 C6 0.1F R1 51 1 C1 47pF TO 1000pF AIN+ R5 1k 1.5VCM R6 1k R2 51 LTC1403A-1 C2 47pF TO 1000pF AIN- 1403A F06a LTC1403-1/LTC1403A-1 APPLICATIO S I FOR ATIO 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 185k 371k 556k FREQUENCY (Hz) 741k 14031 F06b Figure 6b. LTC1403-1 6MHz Sine Wave 4096 Point FFT Plot with the LT1819 Driving the Inputs Differentially Board Layout and Bypassing Wire wrap boards are not recommended for high resolution and/or high speed A/D converters. To obtain the best performance from the LTC1403-1/LTC1403A-1, a printed circuit board with ground plane is required. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track. If optimum phase match between the inputs is desired, the length of the two input wires should be kept matched. High quality tantalum and ceramic bypass capacitors should be used at the VDD and VREF pins as shown in the Block Diagram on the first page of this data sheet. For optimum performance, a 10F surface mount AVX capacitor with a 0.1F ceramic is recommended for the VDD and VREF pins. Alternatively, 10F ceramic chip capacitors such as Murata GRM219R60J106M may be used. The capacitors must be located as close to the pins as possible. The traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible. Figure 7 shows the recommended system ground connections. All analog circuitry grounds should be terminated at the LTC1403-1/LTC1403A-1 GND (Pins 4, 5, 6 and exposed pad). The ground return from the LTC1403-1/ LTC1403A-1 (Pins 4, 5, 6 and exposed pad) to the power supply should be low impedance for noise free operation. MAGNITUDE (dB) U 14031 F07 W U U Figure 7. Recommended Layout Digital circuitry grounds must be connected to the digital supply common. In applications where the ADC data outputs and control signals are connected to a continuously active microprocessor bus, it is possible to get errors in the conversion results. These errors are due to feedthrough from the microprocessor to the successive approximation comparator. The problem can be eliminated by forcing the microprocessor into a Wait state during conversion or by using three-state buffers to isolate the ADC data bus. POWER-DOWN MODES Upon power-up, the LTC1403-1/LTC1403A-1 is initialized to the active state and is ready for conversion. The Nap and Sleep mode waveforms show the power-down modes for the LTC1403-1/LTC1403A-1. The SCK and CONV inputs control the power-down modes (see Timing Diagrams). Two rising edges at CONV, without any intervening rising edges at SCK, put the LTC1403-1/LTC1403A-1 in Nap 14031f 13 LTC1403-1/LTC1403A-1 APPLICATIO S I FOR ATIO mode and the power drain drops from 14mW to 6mW. The internal reference remains powered in Nap mode. One or more rising edges at SCK wake up the LTC1403-1/ LTC1403A-1 for service very quickly, and CONV can start an accurate conversion within a clock cycle. Four rising edges at CONV, without any intervening rising edges at SCK, put the LTC1403-1/LTC1403A-1 in Sleep mode and the power drain drops from 16mW to 10W. One or more rising edges at SCK wake up the LTC1403-1/LTC1403A-1 for operation. The internal reference (VREF ) takes 2ms to slew and settle with a 10F load. Note that, using sleep mode more frequently than every 2ms, compromises the settled accuracy of the internal reference. Note that, for slower conversion rates, the Nap and Sleep modes can be used for substantial reductions in power consumption. DIGITAL INTERFACE The LTC1403-1/LTC1403A-1 has a 3-wire SPI (Serial Protocol Interface) interface. The SCK and CONV inputs and SDO output implement this interface. The SCK and CONV inputs accept swings from 3V logic and are TTL compatible, if the logic swing does not exceed VDD. A detailed description of the three serial port signals follows: Conversion Start Input (CONV) The rising edge of CONV starts a conversion, but subsequent rising edges at CONV are ignored by the LTC1403-1/ LTC1403A-1 until the following 16 SCK rising edges have occurred. It is necessary to have a minimum of 16 rising edges of the clock input SCK between rising edges of CONV. But to obtain maximum conversion speed, it is necessary to allow two more clock periods between conversions to allow 39ns of acquisition time for the internal ADC sample-and-hold circuit. With 16 clock periods per conversion, the maximum conversion rate is limited to 2.8Msps to allow 39ns for acquisition time. In either case, the output data stream comes out within the first 16 clock periods to ensure compatibility with processor serial ports. The duty cycle of CONV can be arbitrarily chosen to be used as a frame sync signal for the processor serial port. A simple approach to generate CONV is to create a pulse that is one SCK wide to drive the LTC1403-1/ LTC1403A-1 and then buffer this signal with the appropriate number of inverters to ensure the correct delay driving 14 U the frame sync input of the processor serial port. It is good practice to drive the LTC1403-1/LTC1403A-1 CONV input first to avoid digital noise interference during the sampleto-hold transition triggered by CONV at the start of conversion. It is also good practice to keep the width of the low portion of the CONV signal greater than 15ns to avoid introducing glitches in the front end of the ADC just before the sample-and-hold goes into hold mode at the rising edge of CONV. Minimizing Jitter on the CONV Input In high speed applications where high amplitude sinewaves above 100kHz are sampled, the CONV signal must have as little jitter as possible (10ps or less). The square wave output of a common crystal clock module usually meets this requirement easily. The challenge is to generate a CONV signal from this crystal clock without jitter corruption from other digital circuits in the system. A clock divider and any gates in the signal path from the crystal clock to the CONV input should not share the same integrated circuit with other parts of the system. As shown in the interface circuit examples, the SCK and CONV inputs should be driven first, with digital buffers used to drive the serial port interface. Also note that the master clock in the DSP may already be corrupted with jitter, even if it comes directly from the DSP crystal. Another problem with high speed processor clocks is that they often use a low cost, low speed crystal (i.e., 10MHz) to generate a fast, but jittery, phase-locked-loop system clock (i.e., 40MHz). The jitter in these PLL-generated high speed clocks can be several nanoseconds. Note that if you choose to use the frame sync signal generated by the DSP port, this signal will have the same jitter of the DSP's master clock. Serial Clock Input (SCK) The rising edge of SCK advances the conversion process and also udpates each bit in the SDO data stream. After CONV rises, the third rising edge of SCK starts clocking out the 12/14 data bits with the MSB sent first. A simple approach is to generate SCK to drive the LTC1403-1/ LTC1403A-1 first and then buffer this signal with the appropriate number of inverters to drive the serial clock input of the processor serial port. Use the falling edge of the clock to latch data from the Serial Data Output (SDO) 14031f W U U LTC1403-1/LTC1403A-1 APPLICATIO S I FOR ATIO into your processor serial port. The 14-bit Serial Data will be received right justified, in a 16-bit word with 16 or more clocks per frame sync. It is good practice to drive the LTC1403-1/LTC1403A-1 SCK input first to avoid digital noise interference during the internal bit comparison decision by the internal high speed comparator. Unlike the CONV input, the SCK input is not sensitive to jitter because the input signal is already sampled and held constant. Serial Data Output (SDO) Upon power-up, the SDO output is automatically reset to the high impedance state. The SDO output remains in high impedance until a new conversion is started. SDO sends out 12/14 bits in 2's complement format in the output data stream beginning at the third rising edge of SCK after the rising edge of CONV. SDO is always in high impedance mode when it is not sending out data bits. Please note the delay specification from SCK to a valid SDO. SDO is always guaranteed to be valid by the next rising edge of SCK. The 16-bit output data stream is compatible with the 16-bit or 32-bit serial port of most processors. 3V VDD 7 10 CONV LTC1403-1/ LTC1403A-1 9 SCK SDO GND 8 6 CONV CLK 3-WIRE SERIAL INTERFACELINK B13 B12 0V TO 3V LOGIC SWING Figure 8. DSP Serial Interface to TMS320C54x U HARDWARE INTERFACE TO TMS320C54x The LTC1403-1/LTC1403A-1 is a serial output ADC whose interface has been designed for high speed buffered serial ports in fast digital signal processors (DSPs). Figure 8 shows an example of this interface using a TMS320C54X. The buffered serial port in the TMS320C54x has direct access to a 2kB segment of memory. The ADC's serial data can be collected in two alternating 1kB segments, in real time, at the full 2.8Msps conversion rate of the LTC1403-1/ LTC1403A-1. The DSP assembly code sets frame sync mode at the BFSR pin to accept an external positive going pulse and the serial clock at the BCLKR pin to accept an external positive edge clock. Buffers near the LTC1403-1/ LTC1403A-1 may be added to drive long tracks to the DSP to prevent corruption of the signal to LTC1403-1/ LTC1403A-1. This configuration is adequate to traverse a typical system board, but source resistors at the buffer outputs and termination resistors at the DSP, may be needed to match the characteristic impedance of very long transmission lines. If you need to terminate the SDO transmission line, buffer it first with one or two 74ACTxx gates. The TTL threshold inputs of the DSP port respond properly to the 3V swing from the SDO pin. 5V VCC BFSR BCLKR BDR TMS320C54x 14031 F08 W U U 14031f 15 LTC1403-1/LTC1403A-1 APPLICATIO S I FOR ATIO ; ; ; ; ; ; ; ; ; ; ; ; ; 10-23-03 ****************************************************************** Files: 014SI.ASM -> 1403 bipolar Sine wave collection with Serial Port interface bvectors.asm buffered mode. s2k14ini.asm 2k buffer size. first element at 1024, last element at 1023, two middles at 2047 and 0000 bipolar mode Works 16 or 64 clock frames. negative edge BCLKR negative BFSR pulse -0 data shifted 1' cable from counter to CONV at DUT 2' cable from counter to CLK at DUT *************************************************************************** .width 160 .length 110 .title "sineb0 BSP in auto buffer mode" .mmregs .setsect ".text", 0x500,0 ;Set address .setsect "vectors", 0x180,0 ;Set address .setsect "buffer", 0x800,0 ;Set address .setsect "result", 0x1800,0 ;Set address .text ;.text marks start: ;this label seems necessary ;Make sure /PWRDWN is low at J1-9 ;to turn off AC01 adc tim=#0fh prd=#0fh tcr = #10h tspc = #0h pmst = #01a0h sp = #0700h dp = #0 ar2 = #1800h ar3 = #0800h ar4 = #0h call sineinit sinepeek: call sineinit wait ; goto wait ; stop timer ; stop TDM serial port to AC01 ; set up iptr. Processor Mode STatus register ; init stack pointer. ; data page ; pointer to computed receive buffer. ; pointer to Buffered Serial Port receive buffer ; reset record counter ; Double clutch the initialization to insure a proper ; reset. The external frame sync must occur 2.5 clocks ; or more after the port comes out of reset. ----------------Buffered Receive Interrupt Routine ------------------ breceive: ifr = #10h ; clear interrupt flags TC = bitf(@BSPCE,#4000h) ; check which half (bspce(bit14)) of buffer if (NTC) goto bufull ; if this still the first half get next half bspce = #(2023h + 08000h); turn on halt for second half (bspce(bit15)) return_enable ; --------------mask and shift input data ---------------------------- bufull: b = *ar3+ << -0 b = #03FFFh & b b = b ^ #2000h *ar2+ = data(#0bh) TC = (@ar2 == #02000h) if (TC) goto start goto bufull ; ; ; ; ; ; load acc b with BSP buffer and shift right -0 mask out the TRISTATE bits with #03FFFh invert the MSB for bipolar operation B store B to out buffer and advance AR2 pointer output buffer is 2k starting at 1800h restart if out buffer is at 1fffh 16 U of executable of incoming 1403 data of BSP buffer for clearing of result for clearing start of code 14031f W U U LTC1403-1/LTC1403A-1 APPLICATIO S I FOR ATIO ; bsend ; ------------------dummy bsend return------------------------ return_enable ;this is also a dummy return to define bsend ;in vector table file BVECTORS.ASM ---------------------- end ISR ---------------------------- .copy "c:\dskplus\1403\s2k14ini.asm" ;initialize buffered serial port .space 16*32 ;clear a chunk at the end to mark the end ;====================================================================== ; ; VECTORS ; ;====================================================================== .sect "vectors" ;The vectors start here .copy "c:\dskplus\1403\bvectors.asm" ;get BSP vectors .sect "buffer" .space 16*0x800 .sect "result" .space 16*0x800 .end ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; *************************************************************************** File: BVECTORS.ASM -> Vector Table for the `C54x DSKplus 10.Jul.96 BSP vectors and Debugger vectors TDM vectors just return *************************************************************************** The vectors in this table can be configured for processing external and internal software interrupts. The DSKplus debugger uses four interrupt vectors. These are RESET, TRAP2, INT2, and HPIINT. * DO NOT MODIFY THESE FOUR VECTORS IF YOU PLAN TO USE THE DEBUGGER * All other vector locations are free to use. When programming always be sure the HPIINT bit is unmasked (IMR=200h) to allow the communications kernel and host PC interact. INT2 should normally be masked (IMR(bit 2) = 0) so that the DSP will not interrupt itself during a HINT. HINT is tied to INT2 externally. ;Set address of BSP buffer for clearing ;Set address of result for clearing .title "Vector Table" .mmregs reset nmi goto #80h nop nop return_enable nop nop nop goto #88h nop nop .space 52*16 return_enable nop nop nop return_enable nop nop nop ;00; RESET * DO NOT MODIFY IF USING DEBUGGER * ;04; non-maskable external interrupt trap2 ;08; trap2 * DO NOT MODIFY IF USING DEBUGGER * int0 ;0C-3F: vectors for software interrupts 18-30 ;40; external interrupt int0 int1 ;44; external interrupt int1 U 14031f W U U 17 LTC1403-1/LTC1403A-1 APPLICATIO S I FOR ATIO int2 return_enable nop nop nop return_enable nop nop nop goto breceive nop nop nop goto bsend nop nop nop return_enable nop nop nop return_enable nop nop return_enable nop nop nop dgoto #0e4h nop nop .space 24*16 ;48; external interrupt int2 tint ;4C; internal timer interrupt brint ;50; BSP receive interrupt bxint ;54; BSP transmit interrupt trint ;58; TDM receive interrupt txint int3 ;5C; TDM transmit interrupt ;60; external interrupt int3 hpiint ;64; HPIint * DO NOT MODIFY IF USING DEBUGGER * ;68-7F; reserved area ********************************************************************** * (C) COPYRIGHT TEXAS INSTRUMENTS, INC. 1996 * ********************************************************************** * * * File: s2k14ini.ASM BSP initialization code for the `C54x DSKplus * * for use with 1403 in buffered mode * * BSPC and SPC are the same in the `C542 * * BSPCE and SPCE seem the same in the `C542 * ********************************************************************** .title "Buffered Serial Port Initialization Routine" ON .set 1 OFF .set !ON YES .set 1 NO .set !YES BIT_8 .set 2 BIT_10 .set 1 BIT_12 .set 3 BIT_16 .set 0 GO .set 0x80 ********************************************************************** * This is an example of how to initialize the Buffered Serial Port (BSP). * The BSP is initialized to require an external CLK and FSX for * operation. The data format is 16-bits, burst mode, with autobuffering * enabled. * 18 U 14031f W U U LTC1403-1/LTC1403A-1 APPLICATIO S I FOR ATIO ***************************************************************************************************** *LTC1403 timing from board with 10MHz crystal. * *10MHz, divided from 40MHz, forced to CLKIN by 1403 board. * *Horizontal scale is 25ns/chr or 100ns period at BCLKR * *Timing measured at DSP pins. Jxx pin labels for jumper cable. * *BFSR Pin J1-20 ~~\____/~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\____/~~~~~~~~~~~* *BCLKR Pin J1-14 _/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~* *BDR Pin J1-26 _--_--_-- Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U 14031f W U U 19 LTC1403-1/LTC1403A-1 PACKAGE DESCRIPTIO 0.254 (.010) GAUGE PLANE DETAIL "A" 0 - 6 TYP 12345 0.53 0.152 (.021 .006) DETAIL "A" 1.10 (.043) MAX 0.18 (.007) NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX RELATED PARTS PART NUMBER ADCs LTC1608 LTC1604 LTC1609 LTC1411 LTC1414 LTC1403/LTC1403A LTC1407/LTC1407A LTC1407-1/LTC1407A-1 LTC1420 LTC1405 LTC1412 LTC1402 LTC1864/LTC1865 DACs LTC1666/LTC1667/LTC1668 LTC1592 References LT1790-2.5 LT1461-2.5 LT1460-2.5 Micropower Series Reference in SOT-23 Precision Voltage Reference Micropower Series Voltage Reference 0.05% Initial Accuracy, 10ppm Drift 0.04% Initial Accuracy, 3ppm Drift 0.1% Initial Accuracy, 10ppm Drift 14031f DESCRIPTION 16-Bit, 500ksps Parallel ADC 16-Bit, 333ksps Parallel ADC 16-Bit, 250ksps Serial ADC 14-Bit, 2.5Msps Parallel ADC 14-Bit, 2.2Msps Parallel ADC 12-/14-Bit, 2.8Msps Serial ADC 12-/14-Bit, 3Msps Simultaneous Sampling ADC 3V, 2-Channel Differential, Unipolar Inputs, 14mW, MSOP Package 12-/14-Bit, 3Msps Simultaneous Sampling ADC 3V, 2-Channel Differential, Bipolar Inputs, 14mW, MSOP Package 12-Bit, 10Msps Parallel ADC 12-Bit, 5Msps Parallel ADC 12-Bit, 3Msps Parallel ADC 12-Bit, 2.2Msps Serial ADC 16-Bit, 250ksps Serial ADC 12-/14-/16-Bit, 50Msps DACs 16-Bit, Serial SoftSpanTM IOUT DAC 5V, Selectable Spans, 72dB SINAD 5V, Selectable Spans, 115mW 5V Supply, 2.5V Span, 72dB SINAD 5V or 5V Supply, 4.096V or 2.5V Span 5V Supply, 1 and 2 Channel, 4.3mW, MSOP Package 87dB SFDR, 20ns Settling Time 1LSB INL/DNL, Software Selectable Spans SoftSpan is a trademark of Linear Technology Corporation. 20 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 q FAX: (408) 434-0507 q U MSE Package 10-Lead Plastic MSOP (Reference LTC DWG # 05-08-1663) 3.00 0.102 (.118 .004) (NOTE 3) 10 9 8 7 6 0.497 0.076 (.0196 .003) REF BOTTOM VIEW OF EXPOSED PAD OPTION 1 2.06 0.102 (.081 .004) 1.83 0.102 (.072 .004) 4.90 0.152 (.193 .006) 3.00 0.102 (.118 .004) (NOTE 4) 10 0.86 (.034) REF 2.794 0.102 (.110 .004) 0.889 0.127 (.035 .005) SEATING PLANE 0.17 - 0.27 (.007 - .011) TYP 0.50 (.0197) BSC 0.127 0.076 (.005 .003) MSOP (MSE) 0603 5.23 (.206) MIN 2.083 0.102 3.20 - 3.45 (.082 .004) (.126 - .136) 0.50 0.305 0.038 (.0197) (.0120 .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT COMMENTS 5V Supply, 2.5V Span, 90dB SINAD 5V Supply, 2.5V Span, 90dB SINAD 5V, Configurable Bipolar/Unipolar Inputs 5V, Selectable Spans, 80dB SINAD 5V Supply, 2.5V Span, 78dB SINAD 3V, 15mW Unipolar Inputs, MSOP Package LT/TP 0404 1K * PRINTED IN USA www.linear.com (c) LINEAR TECHNOLOGY CORPORATION 2004 |
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